1. Field of the Invention
The present invention relates to a synchronizing circuit including a hysteresis phase comparator, more particularly, a PLL (Phase Locked Loop) circuit for generating a clock signal adapted for a system provided with a CODEC (Coder & Decoder) for a voice signal or an audio signal.
2. Description of the Related Art
When data is transmitted with a digital signal from a transmitting side to a receiving side, it is required that the data is correctly received by the receiving side, i.e., the data does not lack a data piece, or it does not contain duplicate data pieces. Furthermore, in a system wherein the received data is finally converted into an analog signal, it is also needed to sufficiently reduce the jitter of a clock on the receiving side which synchronizes with the received data. This need further increases, especially for a system incorporating an audio CODEC or a voice CODEC which handles a voice signal or an audio signal. This is because such a system uses the clock on the receiving side as a sampling clock for an AD converter (ADC) or a DA converter (DAC). That is, when jitter occurs in the clock of the receiving side, the S/N ratio (signal-to-noise ratio) of the ADC or DAC lowers. In general, it is required that the jitter of a clock to be obtained is reduced as the resolution of the ADC or DAC increases.
FIG. 8 shows an example of the structure of a conventional system including a CODEC. The conventional system comprises a signal processing section 10 and a CODEC section 20. The signal processing section 10 processes a digital signal, etc. The CODEC section 20 has a function of converting an analog input signal into a digital signal (first transfer data) and a function of converting a digital signal (second transfer data) output from the signal processing section 10 into an analog output signal. Such a system is used in transmission and reception of voice, etc. by a mobile telephone.
As shown in FIG. 8, the second transfer data is transferred from the signal processing section 10 to the CODEC section 20, and the first transfer data is transferred from the CODEC section 20 to the signal processing section 10. Also, a transfer clock (reference signal) which synchronizes with the first and second transfer data is supplied from the signal processing section 10 to the CODEC section 20.
The CODEC section 20 comprises an I/F (interface) section 21, a CODEC 22 and an analog PLL 23. The analog PLL 23 fetches the transfer clock from the signal processing section 10. The analog PLL 23 generates an I/F clock synchronizing with the transfer clock, and outputs the I/F clock to the I/F section 21. Further, the analog PLL 23 generates a sampling clock having a frequency which is a rational number of times greater than that of the transfer clock, and outputs the sampling clock to the CODEC 22.
The I/F section 21 receives the second transfer data from the signal processing section 10, while synchronizing the second transfer data with the I/F clock from the analog PLL 23. Then, the I/F section 21 generates a reception signal (digital signal) in accordance with the second transfer data, and outputs the reception signal to the CODEC 22. Further, the I/F section 21 receives transmission data (digital signal) from the CODEC 22, while synchronizing the transmission data with the I/F clock from the analog PLL 23. The I/F section 21 then generates the first transfer data in accordance with the transmitted data, and outputs the first transfer data to the signal processing section 10.
The CODEC 22 comprises a digital signal processing circuit and an ADC and DAC. The CODEC 22 converts the reception data from the I/F section 21 into an analog output signal by using the sampling clock from the analog PLL 23.
In such a manner, in the conventional system shown in FIG. 8, A/D conversion is performed by the ADC, or D/A conversion is performed by the DAC, in addition to transmission and reception of data, based on the I/F clock and sampling clock which are generated by the analog PLL 23. Therefore, the characteristics of the analog PLL 23 greatly influence those of the system.
FIG. 9 shows an example of the structure of the analog PLL 23 shown in FIG. 8. The analog PLL 23 comprises a phase comparator 23a, a loop filter 23b, a VCO (Voltage Controlled Oscillator) 23c and a frequency divider 23d. The phase comparator 23a generates a signal in accordance with the phase difference between the I/F clock and the transfer clock from the signal processing section 10, and then supplies the signal to the loop filter 23b. The loop filter 23b smoothens the signal supplied from the phase comparator 23a, and then supplies the signal to the VCO 23c. The VCO 23c generates a signal having a frequency which is determined in accordance with the signal supplied from the loop filter 23b. The signal generated by the VCO 23c is subjected to frequency division by the frequency divider 23d (i.e., its frequency is divided by the frequency divider 23d). The signal subjected to frequency division is then supplied as the I/F clock to the I/F section 21 and the phase comparator 23a. In such a manner, regularly, the analog PLL 23 operates to equalize the transfer clock and the I/F clock, and also to make the phase difference therebetween constant.
FIG. 10 shows another example of the structure of the conventional system including the CODEC. In this example, the system has the same elements as the system shown in FIG. 8, with the exception of the following: the analog PLL 23 is replaced by a digital PLL 23A to which a master clock (MCLK) is input (see, e.g., Troha, James, D. “Digital Phase-Locked Loop Design using SN54/74LS297”, Texas Instruments Application Note, http://www-s.ti.com/sc/psheets/sdla005b/sdla005b.pdf, 1997, which discloses an example of the digital PLL).
The MCLK is a clock signal generated within a CODEC section 20′ or a clock signal supplied from the outside of the CODEC section 20′. The frequency of the MCLK is an integer number of times greater than the average frequency of the I/F clock.
FIG. 11 shows an example of the structure of the digital PLL 23A shown in FIG. 10. The digital PLL 23A comprises a phase comparator 23a, a frequency divider 23d, a digital loop filter 23e and a variable frequency divider 23f. In the digital PLL 23A, the digital loop filter 23e and the variable frequency divider 23f are used, instead of the loop filter 23b and VOC 23c of the analog PLL 23, respectively. To be more specific, the digital loop filter 23e is a digital filter which operates in accordance with the MCLK. The digital loop filter 23e smoothens the output signal of the phase comparator 23a by using the MCLK, and then supplies the signal to the variable frequency divider 23f. The digital loop filter 23e corresponds to the loop filter 23b of the analog PLL 23. The variable frequency divider 23f is a frequency divider the frequency division ratio of which varies in accordance with the output signal of the digital loop filter 23e. More specifically, the variable frequency divider 23f divides the frequency of the MCLK at the frequency division ratio which is controlled by the digital loop filter 23e, and generates a sampling clock. The variable frequency divider 23f then outputs the sampling clock to the frequency divider 23d and the CODEC 22. The variable frequency divider 23f corresponds to the VCO 23c of the analog PLL 23. As can be seen from the above, the digital PLL 23A is substantially equivalent to the analog PLL 23.
As explained above, with respect to the system provided with the CODEC, the system using the digital PLL 23A is substantially equivalent to that using the analog PLL 23. Accordingly, with respect to those systems, the following explanation is given by referring to only the system using the analog PLL 23 shown in FIG. 8 and the analog PLL 23 in FIG. 9. Needless to say, even if they are replaced by the system using the digital PLL 23A shown in FIG. 10 and the digital PLL 23A in FIG. 11, the same explanation can be applied.
FIGS. 12A to 12D show examples of the waveforms of signals used in the system shown in FIG. 8. To be more specific, FIGS. 12A, 12B, 12C and 12D disclose the transfer clock, the second transfer data, the I/F clock and the reception data, respectively. The signal level of the second transfer data varies in synchronism with the rising edge of the transfer clock. The rising edge of the I/F clock is synchronized with the falling edge of the transfer clock by the analog PLL 23. It is shown in the above figures that the period from time t3 to time t4 of the transfer clock is longer than any of the other periods thereof. The I/F clock varies while following the transfer clock in period, and the period from time t3i to t4i of the I/F clock is longer than any of the other periods thereof. In such a manner, the system in FIG. 8 generates an I/F clock, which varies while following variation of the transfer clock with respect to period, by using the analog PLL 23, thereby achieving reliable data transfer.
As explained above, in the system in FIG. 8, the periods of the I/F clock are not constant. This means that the transfer clock has jitter, and the I/F clock thus also has jitter. This means that jitter also occurs in a sampling clock having a frequency which is a rational number of times greater than that of the transfer clock. Accordingly, as stated above, the S/N ratio of the ADC or DAC of the CODEC 22 lowers.
FIG. 13 shows a relationship between the phase difference between two signals (the transfer clock and I/F clock) input to the phase comparator 23a of the analog PLL 23 (which is referred to as an input signal phase difference in the figure) and the variation of the frequency of the output signal from the analog PLL 23 (which is referred to as an output frequency variation in the figure). As shown in FIG. 13, the analog PLL 23 is designed such that the output signal frequency increases in a monotonically increasing manner as the phase difference between the signals input to the phase comparator 23a increases. If the frequency of the output signal does not vary when the phase difference between the input signals is within a certain range, the range is referred to as a dead zone. Referring to FIG. 13, when the variation of the frequency of the output signal is “0”, the phase difference between the input signals is also “0”. However, generally, the above phenomenon is not limited to the case where the phase difference is “0” when the frequency variation is “0”. That is, generally, in this case the phase difference is not necessarily “0”, and it is constant.
As is clear from FIG. 13, one of the features of a conventional PLL circuit resides in that the greater the phase difference between the input signals, the greater the variation of the frequency of the output signal. When this is explained with respect to the system in FIG. 8, it can be said that the frequency variation of each of the I/F clock and the sampling clock increases as the variation of the phase of the transfer clock increases. In other words, jitter occurs in the I/F clock and the sampling clock when the level of the jitter of the transfer clock increases. That is, it can be considered that use of the conventional analog PLL 23 easily causes lowering of the S/N ratio of the CODEC 22.
The total characteristics of the analog PLL 23 also depend on transient response characteristics thereof. FIGS. 14 and 15 show examples of the transient response characteristics when the output frequency of the analog PLL 23 changes from f1 to f2. FIG. 14 shows a case where a lock-up time is short, but relatively large overshoot and undershoot (ringing) occur. FIG. 15 shows a case where the overshoot is small, but the lock-up time is long. Also, it should be noted that suppose the lock-up time is a time period required until the output frequency falls within an allowable error range as shown in, e.g., FIGS. 14 and 15. It is known that the total characteristics of the analog PLL23 depend on conversion characteristics of the phase comparator 23a, characteristics of the oscillation frequency of the VCO 23c to a control signal and characteristics of the loop filter 23.
Generally, as shown in FIGS. 14 and 15, when the lock-up time is short, overshoot or undershoot easily occurs. On the other hand, when the overshoot or undershoot is small, the lock-up time tends to be long.
FIGS. 16A to 16C show examples of the frequency variation of the transfer clock, and examples of the frequency variation of the I/F clock to that of the transfer clock. FIG. 16A is an example of the frequency variation of the transfer clock. “EXAMPLE 1 OF FREQUENCY VARIATION OF I/F CLOCK” in FIG. 16B is an example of the case where an analog PLL having such transient response characteristics as shown in FIG. 14 is used as the analog PLL 23. “EXAMPLE 2 OF FREQUENCY VARIATION OF I/F CLOCK” in FIG. 16C is an example of the case where an analog PLL having such transient response characteristics as shown in FIG. 15 is used as the analog PLL 23.
In “EXAMPLE 2 OF FREQUENCY VARIATION OF I/F CLOCK” in FIG. 16C, the frequency does not steeply or minutely vary, and the frequency variation is relatively smooth, as compared with “EXAMPLE 1 OF FREQUENCY VARIATION OF I/F CLOCK” in FIG. 16B. However, EXAMPLE 1 and EXAMPLE 2 have both the same problem. That is, in EXAMPLE 1 and EXAMPLE 2, the frequency of the I/F clock varies while following variation of the frequency of the transfer clock.
In the system in FIG. 8, it is preferable that the lock-up time be short, in order to ensure reliable data transfer. Thus, as the analog PLL 23, the analog PLL having such transient response characteristics as shown in FIG. 14 is more suitable than the analog PLL having such transient response characteristics as shown in FIG. 15. However, when the analog PLL having transient response characteristics shown in FIG. 14 is used as the analog PLL 23, the output frequency easily shows minute variation due to overshoot and undershoot as shown in FIG. 16B. Even if the frequency of the transfer clock varies by such a slight amount as not to affect the data transfer, the frequency of the analog output signal varies inevitably.
In such a manner, there is a case where as the function (characteristics) of the PLL circuit varies, the jitter increases, and the S/N ratio of the CODEC further lowers.
As explained above, in the above conventional method, the I/F clock reliably follows the transfer track, thus achieving reliable data transfer. However, when the conventional method is applied to a system provided with a voice CODEC or an audio CODEC, the S/N ratio lowers.
It should be noted that there is a method which can satisfy both the above two requirements in which reliable data transfer is achieved, and the S/N ratio is not lowered. However, if the method is applied, the circuit is complicated, as compared with the case where the above conventional method is applied. It is thus also inappropriate.
Namely, it is required to reduce the size of the circuit and the power consumption as much as possible, and provide a system which satisfies the above requirements and can be easily achieved.